1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device that uses three-dimensionally formed transistors or thyristors and a method of manufacturing the same.
2. Description of Related Art
The scale of integration of semiconductor devices has conventionally been enhanced mostly by miniaturizing transistors. The miniaturization of the transistors is already reaching its limit, and a further reduction in transistor size may possibly hinder proper operation due to a short channel effect etc.
As a fundamental solution to such a problem, there have been proposed methods for spatially processing a semiconductor substrate to form the transistors in a three-dimensional fashion. In particular, three-dimensional transistors that use silicon pillars extending in a direction perpendicular to the main surface of the semiconductor substrate as their channels have the advantages of having a small area of occupancy and providing a high drain current because of complete depletion. A closest-packed layout of 4F2 (F is the minimum processing size) is also available (see Jpn. Pat. Appln. Laid-Open Publication No. 2009-010366).
Conventionally, semiconductor devices, or a DRAM (Dynamic Random Access Memory) in particular, have typically used capacitors for information storage. The enhanced scale of integration miniaturizes the capacitors, making it difficult to secure the capacitances of the capacitors. There has recently been proposed a capacitorless DRAM in which memory cells are formed without a capacitor. U.S. Pat. Appln. Publication No. 2009-0213648 discloses an example of a capacitorless DRAM which is composed of three-dimensionally formed thyristors.